Method to control d-ff circuit

ABSTRACT

An input buffer chooses, in accordance with first control clocks, to output an input data signal or output a high-impedance signal. A master flip-flop chooses, in accordance with second control clocks, to output a data signal received from the input buffer or retain a currently output data signal. A master-slave switch chooses, in accordance with the second control clocks, to output a high-impedance signal or output a data signal received from the master flip-flop. A slave flip-flop chooses, in accordance with the second control clocks, to retain a currently output data signal or output a data signal received from the master-slave switch. A clock buffer inputs the second control clocks, and generates and outputs the first control clocks.

BACKGROUND

The present invention relates to a semiconductor integrated circuit, andmore particularly to a master-slave flip-flop circuit.

In recent years, an LCD driver capable of operating at a high speed isdemanded as liquid-crystal panel displays exhibit improved motionpicture response. The speed of the LCD driver can be increased, forinstance, by shortening the propagation delay time tpd of a flip-flopcircuit (hereinafter referred to as the FF circuit) used in the LCDdriver. It is also demanded that the FF circuit of a video signal inputstage operate at an increased speed as an input video signal for the LCDdriver is serialized. Consequently, it is demanded that the propagationdelay time tpd be shortened while setup time and hold time, whichdetermine the skew between an input signal and a clock signal, can beoptimally adjusted.

Particularly when the employed transmission method is such that a clocksignal is embedded in a serial data signal, the active edge of a clockgenerated by a clock recovery circuit coincides in time with a datasignal change point. It is therefore important that mainly the setuptime be secured. The reason is that if an attempt is made to secure along setup time by adjusting the phase of the clock recovery circuit,the hold time, which is difficult to control, cannot be sufficientlysecured due to the active edge of the next clock.

A technology for increasing the operating speed of the FF circuit isdescribed, for instance, in Japanese Unexamined Patent Publication No.2001-237675. A D-FF circuit described in Japanese Unexamined PatentPublication No. 2001-237675 is a master-slave D-FF circuit. This circuitcan retard the operation stop clock of a master FF and advance theoperation start clock of a slave FF to shorten the setup time whilemaintaining the propagation delay time tpd.

FIG. 1 is a diagram illustrating the configuration of the D-FF circuitdescribed in Japanese Unexamined Patent Publication No. 2001-237675.Referring to FIG. 1, the D-FF circuit described in Japanese UnexaminedPatent Publication No. 2001-237675 includes a master FF 100, an inputcontrol switch G1 for controlling the input of data DATA into the masterFF 100, an input control switch G3 for controlling the input of dataoutput from the master FF 100 into a slave FF 200, and a slave FF 200.The master FF 100 includes a feedback control switch G2 for latchinginput data DATA. The slave FF 200 includes a feedback control switch G4for latching input data.

The input control switch G1 and the feedback control switch G2 operatein synchronism with control clocks CLK2, /CLK2. The input control switchG3 and the feedback control switch G4 operate in synchronism withcontrol clocks CLK, /CLK1. A clock generator circuit 300 shown in FIG. 2generates the control clocks CLK, /CLK1, CLK2, /CLK2 from a clock CLK.

Referring to FIG. 2, the clock generator circuit 300 (switch controlcircuit) includes an inverter 301, a buffer 302, and an inverter 303,which are cascade-coupled and arranged in the order named from the inputside. The clock CLK is output as the clock/CLK1 through the inverter301. The clock/CLK1 is output as the clock/CLK2 through the buffer 302.The clock/CLK2 is output as the clock CLK2 through the inverter 303. Inother words, the clocks CLK2, /CLK2 are generated by retarding theclocks CLK, /CLK1.

The input control switch G1 for transmitting an input signal to themaster FF 100 and the feedback control switch G2 for the master FF 100start operating and stop in synchronism with the clocks CLK2, /CLK2whose timings are retarded from the timing of the input control switchG3, which transmits an input signal to the slave FF 200. Therefore, thetiming at which data (internal data) is loaded from the master FF 100into the slave FF 200 is retarded. Consequently, the setup time isshorter than for the D-FF circuit, which controls the master FF andslave FF with the clock CLK alone. Meanwhile, the propagation delay timetpd is determined in accordance with the through operation start time ofthe slave FF 200, which operates in accordance with the clock CLK.Therefore, the setup time is shortened without changing the propagationdelay time tpd. Hence, the D-FF circuit described in Japanese UnexaminedPatent Publication No. 2001-237675 can shorten the setup time whilemaintaining the propagation delay time tpd.

SUMMARY

To improve the setup time while shortening the propagation delay timetpd, it is necessary to advance the change point for the data DATArelative to the active edge of the clock CLK, which controls the inputcontrol switch for transmitting an input signal to the master FF, orretard the active edge of the clock CLK, which controls the inputcontrol switch, relative to the change point for the data DATA.

For example, the data DATA can be advanced relative to the clock CLK,which controls the input control switch, by increasing the gate width(W) of a transistor that forms the input control switch. However, if thegate size of the transistor is increased, the output load capacitance ofthe switch control circuit (clock buffer), which drives the inputcontrol switch, is increased to dull the signal waveform of the clockCLK. Further, if the size (driving force) of the clock buffer isincreased to prevent the signal waveform from being dulled, the clockCLK is advanced relative to the data DATA so that the setup time cannotbe adjusted.

If, on the other hand, the driving force of the clock buffer isdecreased to retard the clock relative to the data, the propagationdelay time tpd of the whole FF circuit is increased.

As described above, it is difficult to make such adjustments as toshorten the propagation delay time tpd in the FF circuit while improvingthe setup time.

The D-FF circuit described in Japanese Unexamined Patent Publication No.2001-237675 can improve the setup time while maintaining the propagationdelay time tpd. However, if it attempts to shorten the propagation delaytime by increasing the speed of data transfer and adjust the setup timefor speed enhancement, the following problem occurs:

If the gate size of a transistor for the input control switch G1 isincreased, the load capacitance coupled to the output of the clockbuffer (inverter 303 and buffer 302), which controls the input controlswitch G1, is increased to dull the signal waveforms of the clocks CLK2,/CLK2. To prevent the signal waveforms from being dulled, it isnecessary to increase the driving capacity of the inverter 303 and thebuffer 302. However, the load capacitance coupled to the inverter 303and buffer 302 corresponds to the sum of the input control switch G1 andfeedback control switch G2. Therefore, the sizes of the inverter 303 andbuffer 302 need to be adjusted to match the total load capacitance. Inother words, if the technology described in Japanese Unexamined PatentPublication No. 2001-237675 is used to shorten the rise time and falltime of the clocks CLK2, /CLK2 for the purpose of data speedenhancement, the size of a transistor for the inverter 303 and buffer302 needs to be unduly increased. This will increase the layout size ofthe D-FF circuit.

Further, in recent years, an FF circuit capable of transferring data ata speed higher than a process-specific operating speed is demanded dueto an increase in the speed of LCD drivers and a trend toward serialtransmission of input video signals and lower power consumption. Whenthe timings of the clocks CLK2, /CLK2 are to be adjusted with the D-FFcircuit described in Japanese Unexamined Patent Publication No.2001-237675, it is necessary to consider the total load capacitance ofthe input control switch G1 and feedback control switch G2.Consequently, it is difficult for the related art technology to maketiming adjustments in accordance with high-speed data. Hence, a D-FFcircuit capable of making timing adjustments with increased efficiencyis now demanded.

In order to address the above-mentioned problem, the present inventionemploys the following means. In order to clarify the correspondencebetween “WHAT IS CLAIMED IS” and “DETAILED DESCRIPTION,” technicalmatters concerning the means are expressed with the aid of numerals andsymbols, which are used under “DETAILED DESCRIPTION.” However, thenumerals and symbols should not be used to restrictively interpret thetechnical scope of the present invention, which is defined under “WHATIS CLAIMED IS.”

A semiconductor integrated circuit according to an aspect of the presentinvention includes a D-FF circuit and clock buffers (103, 104). The D-FFcircuit includes an input buffer (1), a master flip-flop (2), amaster-slave switch (3), and a slave flip-flop (4). In accordance withfirst control clocks (N3, N4), the input buffer (1) chooses to output aninput data signal (DATA) or output a high-impedance (Hi-Z) signal. Inaccordance with second control clocks (N1, N2), the master flip-flop (2)chooses to output a data signal received from the input buffer (1) orretain a currently output data signal. In accordance with the secondcontrol clocks (N1, N2), the master-slave switch (3) chooses to output ahigh-impedance (Hi-Z) signal or output a data signal output from themaster flip-flop (2). In accordance with the second control clocks (N1,N2), the slave flip-flop (4) chooses to retain a currently output datasignal or output a data signal received from the master-slave switch(3). The clock buffers (103, 104) input the second control clocks (N1,N2), and generate and output the first control clocks (N3, N4).

According to another aspect of the present invention, load capacitanceas viewed from the clock buffers (103, 104), which generates the firstcontrol clocks for controlling the input buffer (1), is not coupled tothe master flip-flop (2), master-slave switch (3), or slave flip-flop(4). Therefore, the load capacitance can be smaller than in the past.Consequently, an increase in the sizes of the clock buffers can beinhibited even when the gate width of a transistor forming the inputbuffer (1) is increased to shorten the delay time in the input buffer(1). Further, the output load on the clock buffers is limited to theinput buffer. Therefore, the timing of only the input buffer can bechanged without affecting the other timings by adjusting the clockbuffers (103, 104), which serve as delay elements for setup timeadjustment. This makes it easy to adjust the setup time and propagationdelay time.

According to the aspects of the present invention, it is made easy toadjust the timing of the D-FF circuit.

In addition, it is possible to adjust the timing of the D-FF circuitwhile suppressing an increase in circuit area.

BRIEF DESCRIPTION OF THE DRAWINGS

Preferred Embodiments of the present invention will be described indetail based on the following figures, in which:

FIG. 1 is a diagram illustrating an example configuration of a D-FFcircuit according to a related art;

FIG. 2 is a diagram illustrating an example configuration of a clockgenerator circuit according to a related art;

FIG. 3 is a diagram illustrating an example configuration of a D-FFcircuit according to an embodiment of the present invention;

FIG. 4 is a diagram illustrating an example configuration of a clockgenerator circuit according to an embodiment of the present invention;

FIGS. 5A and 5B are timing diagrams illustrating exemplary data transferoperations for the purpose of depicting a setup time improvementmechanism of the D-FF circuit according to an embodiment of the presentinvention;

FIG. 6 is a diagram illustrating an example configuration of a switchcontrol circuit according to an embodiment of the present invention; and

FIG. 7 is a diagram illustrating another example configuration of theD-FF circuit according to an embodiment of the present invention.

DETAILED DESCRIPTION

Preferred Embodiments of the present invention will now be describedwith reference to the accompanying drawings. In the drawings, identical,similar, or equivalent elements are designated by identical or similarreference numerals.

(Configuration of D-FF Circuit)

A semiconductor integrated circuit according to an embodiment of thepresent invention includes a master-slave D-FF circuit, which is shownin FIG. 3, and a switch control circuit 10, which is shown in FIG. 4.FIG. 3 is a diagram illustrating an example configuration of the D-FFcircuit. Referring to FIG. 3, the D-FF circuit includes an input buffer1, a master FF 2, a master-slave switch 3 (hereinafter referred to asthe M-S switch 3), a slave FF 4, and an output buffer 5.

Data DATA input into the D-FF circuit is input into the master FF 2through the input buffer 1. Data Qm output from the master FF 2 is inputinto the slave FF 4 through the M-S switch 3. Output data generated bythe slave FF 4 is output as data OUT through the output buffer 5.

The input buffer 1 shown in FIG. 3 includes an inverter 11 and a CMOStransfer gate 12. The inverter 11 inverts the signal level (logic value)of input data and outputs the inverted logic value to the CMOS transfergate 12. In accordance with control clocks N3, N4, which arecomplementary to each other, the CMOS transfer gate 12 controls a signaltransmission between the output of the inverter 11 and the master FF 2(input terminal Nin). More specifically, the CMOS transfer gate 12includes an N-channel MOS transistor and a P-channel MOS transistor. Thesources and drains of these transistors are coupled to each other toform input and output terminals. The N-channel MOS transistor inputs thecontrol clock N3 at its gate, whereas the P-channel MOS transistorinputs the control clock N4 at its gate. When the control clock N3 is ata high level (hereinafter referred to as the “H” level) and the controlclock N4 is at a low level (hereinafter referred to as the “L” level),the CMOS transfer gate 12 turns on and outputs output data received fromthe inverter 11 to the input terminal Nin of the master FF 2. Further,when the control clock N3 is at the “L” level and the control clock N4is at the “H” level, the CMOS transfer gate 12 turns off and blocks thesignal transmission between the output of the inverter 11 and the inputterminal Nin. While the signal transmission is blocked by the CMOStransfer gate 12, it can be said that a high-impedance (hereinafterreferred to as “Hi-Z”) output is generated from the CMOS transfer gate12.

The master FF 2 shown in FIG. 3 includes a NAND circuit 21, an inverter22, and a CMOS transfer gate 23. The NAND circuit 21 outputs the NAND ofan output signal from the input buffer 1 and the signal level (logicvalue) of a set signal SB to the M-S switch 3 as internal data Qm. Theinternal data Qm output from the NAND circuit 21 is fed back to theinput terminal Nin through the inverter 22 and CMOS transfer gate 23.Setting the set signal at the “L” level sets the internal data Qm of themaster FF 2 at the “H” level asynchronously.

The CMOS transfer gate 23 controls the signal transmission between theoutput of the inverter 22 and the input terminal Nin of the master FF 2in accordance with control clocks N1, N2, which are complementary toeach other. More specifically, the CMOS transfer gate 23 has the samecircuit configuration as the CMOS transfer gate 12. The control clock N1is input into the gate of the N-channel MOS transistor, whereas thecontrol clock N2 is input into the gate of the P-channel MOS transistor.When the control clock N1 is at the “H” level and the control clock N2is at the “L” level, the CMOS transfer gate 23 turns on. The internaldata Qm is then inverted by the inverter 22 and output (fed back) to theinput terminal Nin of the master FF 2. Further, when the control clockN1 is at the “L” level and the control clock N2 is at the “H” level, theCMOS transfer gate 23 turns off, blocks the signal transmission from theoutput of the inverter 22 to the input terminal Nin, and generates a“Hi-Z” output.

The control clock N2 and control clock N4 are substantiallycomplementary to each other, and the control clock N1 and control clockN3 are also substantially complementary to each other. Therefore, whenthe CMOS transfer gate 12 is on, the CMOS transfer gate 23 is off sothat input data DATA is loaded into the master FF 2. When, on the otherhand, the CMOS transfer gate 12 is off, the CMOS transfer gate 23 is onso that loaded data Qm is retained (stored) in the master FF 2.

The M-S switch 3 shown in FIG. 3 includes a CMOS transfer gate 30, whichcontrols the input of the internal data Qm from the master FF 2 to theslave FF 4. More specifically, the CMOS transfer gate 30 has the samecircuit configuration and the same clock signal coupling to the gate asthe CMOS transfer gate 23. When the control clock N1 is at the “H” leveland the control clock N2 is at the “L” level, the CMOS transfer gate 30turns on and outputs the internal data Qm output from the master FF 2 tothe input terminal of the slave FF 4. Further, when the control clock N1is at the “L” level and the control clock N2 is at the “H” level, theCMOS transfer gate 30 turns off, blocks the signal transmission from theoutput of the master FF 2 to the input of the slave FF 4, and generatesa “Hi-Z” output.

The slave FF 4 shown in FIG. 3 includes a NAND circuit 41, an inverter42, and a CMOS transfer gate 43. The NAND circuit 41 outputs the NAND ofan output generated from the master FF 2 through the M-S switch 3 andthe signal level (logic value) of a reset signal RB (the term “RB” is anacronym for “reset bar”) to the output buffer 5. A signal output fromthe NAND circuit 41 is fed back to the input of the NAND circuit 41through the inverter 42 and CMOS transfer gate 43. Setting the resetsignal RB at the “L” level sets output data OUT at the “L” levelasynchronously.

The CMOS transfer gate 43 controls the signal transmission between theoutput of the inverter 42 and the input terminal of the slave FF 4 (theinput of the NAND circuit 41) in accordance with the control clocks N2,N1, which are complementary to each other. More specifically, when thecontrol clock N2 is at the “H” level and the control clock N1 is at the“L” level, the CMOS transfer gate 43 turns on to output (feed back) theinverted output of the NAND circuit 41 to the input of the slave FF 4.Further, when the control clock N2 is at the “L” level and the controlclock N1 is at the “H” level, the CMOS transfer gate 43 turns off toblock the signal transmission from the output of the inverter 42 to theinput of the NAND circuit 41.

When the CMOS transfer gate 30 is on, the CMOS transfer gate 43 is offso that the internal data Qm input from the master FF 2 is loaded intothe slave FF 4. When the CMOS transfer gate 30 is off, the CMOS transfergate 43 is on so that the loaded internal data Qm is retained (stored)in the slave FF 4.

As described above, in the D-FF circuit according to an embodiment ofthe present invention, the opening and closing of an input controlswitch (the CMOS transfer gate 12 shown in FIG. 3) that controls theloading of data DATA into the master FF 2 is controlled by the controlclocks N3, N4, which differ from the control clocks N1, N2 that controlthe opening and closing of the other switches. Consequently, theopening/closing timing of the input control switch (CMOS transfer gate12) for the master FF 2 can be adjusted independently of the otherswitches. The other switches are a feedback control switch (the CMOStransfer gate 23 shown in FIG. 3) for controlling the selection of astorage mode in which the internal data Qm is retained in the master FF2, an input control switch (the CMOS transfer gate 30 shown in FIG. 3)for controlling the loading of the internal data Qm into the slave FF 4,and a feedback control switch (the CMOS transfer gate 43 shown in FIG.3) for controlling the selection of a storage mode in which the outputvalue of the slave FF 4 is retained in the slave FF 4.

The switching timing of each switch in the D-FF circuit according to anembodiment of the present invention is controlled by the switch controlcircuit 10 shown, for instance, in FIG. 4. FIG. 4 is a diagramillustrating an example configuration of the switch control circuitaccording to an embodiment of the present invention. Referring to FIG.4, the switch control circuit 10 includes inverters 101, 102, 103, 104and generates the control clocks N1, N2, N3, and N4 in accordance withan input clock CLK.

More specifically, the inverter 101 inverts the signal level of theinput clock CLK, and outputs the inverted clock to the inverters 102,104 and D-FF circuit as the control clock N2. The inverter 102 invertsthe signal level of the input control clock N2, and outputs the invertedclock to the inverter 103 and D-FF circuit as the control clock N1. Theinverter 103 inverts the signal level of the input control clock N1, andoutputs the inverted clock to the D-FF circuit as the control clock N3.The inverter 104 inverts the signal level of the input control clock N2,and outputs the inverted clock to the D-FF circuit as the control clockN4.

In the switch control circuit 10 according to an embodiment of thepresent invention, a pair of control clocks N1, N2, which arecomplementary to each other, are input into the inverters 103, 104 togenerate another pair of control clocks N3, N4, which are alsocomplementary to each other. Therefore, the timings of the controlclocks N3, N4 can be adjusted by adjusting only the driving capacitiesof the inverters 103, 104.

Further, the outputs of the inverters 103, 104 are coupled to the CMOStransfer gate 12, but are not coupled to the other control switches(CMOS transfer gates 23, 30, 43). It means that the outputs of theinverters 103, 104 are not affected by the load capacitances provided bythe other control switches. Therefore, when the driving forces of theinverters 103, 104 are to be adjusted, only the load capacitanceprovided by the CMOS transfer gate 12 needs to be taken intoconsideration. Conversely, changes in the driving capacities of theinverters 103, 104 would not affect the timings of the other controlclocks N1, N2. In other words, the driving capacities of the inverters103, 104 can be adjusted independently.

The inventors have found that when only the timing at which the dataDATA is loaded into the input buffer 1 is adjusted, the timing of theD-FF circuit can be adjusted in accordance with the speed of the dataDATA even if the timings of the other switches (the timing of dataretention in the master FF 2 and the timings of loading and retainingthe internal data Qm) are not adjusted. In an embodiment of the presentinvention, therefore, the opening and closing of the input controlswitch (CMOS transfer gate 12) for controlling the loading of data DATAinto the master FF 2 can be adjusted independently of the other switches(CMOS transfer gates 23, 30, 43). Further, when the opening/closingtiming of the input control switch (CMOS transfer gate 12) is to beadjusted, only the inverters 103, 104 need to be adjusted withoutconsidering the load capacitances provided by the other switches.Consequently, the present invention ensures that the timing adjustmentsof the D-FF circuit can be made more efficiently (more easily) thanever.

(Operations)

A setup time improvement mechanism of the D-FF circuit according to anembodiment of the present invention will now be described with referenceto FIGS. 5A and 5B. As an example, the D-FF circuit operating at therising edge is described below. For the sake of brevity of explanation,it is assumed in the following description that the phase differencebetween the control clock N1 and the control clock N2, which arecomplementary to each other, is negligible, and that the phasedifference between the control clock N3 and the control clock N4, whichare also complementary to each other, is also negligible.

FIG. 5A is a timing diagram illustrating an exemplary data transferoperation that is performed before the timing adjustments of the D-FFcircuit according to an embodiment of the present invention. Referringto FIG. 5A, it is assumed that the setup time Tstp required for theloading of data DATA is “Tstp1,” and that the time interval between thetime of conversion of the data DATA and the active edges of the controlclocks N3, N4 at which the CMOS transfer gate 12 starts operating is“Tda1.” When “Tstp1” is longer than “Tda1,” the data DATA may not beloaded into the D-FF circuit because the setup time required for theloading of the data DATA is not secured.

However, when the setup time Tstp required for the loading of the dataDATA is shortened to “Tstp2,” which is shorter than “Tda1,” the dataDATA can be successfully loaded to permit the D-FF circuit handlehigh-speed data.

To shorten the setup time Tstp, which is required for the loading of thedata DATA, to “Tstp2,” it is necessary to increase the gate width W of atransistor included in the CMOS transfer gate 12. However, if theabove-mentioned transistor gate width is increased, the output loadcapacitance of the switch control circuit 10, which drives the CMOStransfer gate 12, is increased to dull the control clocks N3, N4. Toavoid such a situation, the present invention increases the drivingcapacity of the clock buffers (inverters 103, 104) by increasing thegate width W of transistors included in the inverters 103, 104. Thisdecreases the load capacitance as viewed from the clock buffers(inverters 103, 104). In this instance, the control clocks N3, N4 arenot output to the other control switches (CMOS transfer gates 23, 30,43). Therefore, the timing adjustments can be made without consideringthe operations performed relative to the other control switches.

In an embodiment of the present invention, the setup time required forthe loading of the data DATA can be adjusted without changing thedriving capacities of the clock buffers (inverters 101, 102), whichoutput the control clocks N1, N2. In other words, the timing adjustmentscan be made so as to handle high-speed data without increasing the sizesof the clock buffers (inverters 101, 102), which output the controlclocks N1, N2.

Further, when timing adjustments are to be made in order to transferhigh-speed data, the setup time can be secured by dulling the waveformsof the control clocks N3, N4. FIG. 5B is a timing diagram illustratingthe waveforms of the control clocks N3, N4 that are obtained aftertiming adjustments. Referring to FIG. 5B, the time interval between thetime of conversion of the data DATA and the active edges of the controlclocks N3, N4 at which the CMOS transfer gate 12 starts operating ischanged to “Tda2,” which is longer than the required setup time Tstp1,by dulling the waveforms of the control clocks N3, N4. This ensures thatthe required setup time is secured even when high-speed data is handled.

When the control clocks N3, N4 are to be retarded as shown in FIG. 5B,the gate widths of transistors included in the clock buffers (inverters103, 104) should be decreased. In this instance, the control clocks N3,N4 are not output to the other control switches (CMOS transfer gates 23,30, 43). Therefore, the timing adjustments can be made withoutconsidering the operations performed relative to the other controlswitches.

Further, when the control clocks N3, N4 are to be retarded, as is thecase with the above paragraph, the setup time required for the loadingof the data DATA can be adjusted without changing the driving capacitiesof the clock buffers (inverters 101, 102), which output the controlclocks N1, N2. In other words, the timing adjustments can be made so asto handle high-speed data without changing the sizes of the clockbuffers (inverters 101, 102), which output the control clocks N1, N2.

The propagation delay time tpd of the D-FF circuit according to anembodiment of the present invention is determined by the control clocksN1, N2 and is not dependent on the control clocks N3, N4, whichdetermine the loading timing of the data DATA. Hence, the propagationdelay time tpd of the D-FF circuit remains unaffected even when thecontrol clocks N3, N4 are adjusted in order to adjust the setup time. Inother words, the present invention makes it possible to improve thesetup time without having to consider the influence upon the propagationdelay time tpd of the D-FF circuit.

In an embodiment of the present invention, the outputs of the clockbuffers (inverters 103, 104) are not coupled to the master FF 2, M-Sswitch 3, or slave FF 4, but are coupled only to the input controlswitch (the CMOS transfer gate 12 in the present example) of the inputbuffer 1. According to an embodiment of the present invention,therefore, the waveforms of the control clocks N3, N4 can be adjustedwithout considering the load capacitances provided by control switches(CMOS transfer gates 23, 30, 43) other than the input control switch(CMOS transfer gate 12) of the input buffer 1. Conversely, even if thewaveforms of the control clocks N3, N4 are adjusted, the timings of theother control clocks N1, N2 remain unaffected. It means that the controlclocks N3, N4 can be adjusted independently. Hence, the waveforms of thecontrol clocks N3, N4 can be adjusted in accordance with an increase inthe speed of the clock CLK without unduly changing the sizes of theclock buffers (inverters 103, 104). Consequently, the timing adjustmentscan be made to cope with speed enhancement more efficiently (moreeasily) than ever.

As described above, in the master-slave D-FF according to an embodimentof the present invention, the clock buffers used to generate the controlclocks N3, N4, which control the loading of the data signal DATA intothe master FF 2, are different from the clock buffers used to generatethe control clocks N1, N2, which control the retention of data in themaster FF 2 and the loading of data into and the retention of data inthe slave FF 4. Therefore, the timings of the control clocks N3, N4,which control a data input control switch for the master FF 2, can beadjusted without considering the load capacitances provided by the othercontrol switches. This not only facilitates the timing adjustments ofthe master-slave D-FF but also prevents an undue increase in the sizesof the clock buffers.

Although only specific embodiments of the present invention have beendescribed in detail, the present invention is not limited thereto but ismeant to include all embodiments modified within the spirit of thepresent invention. For example, the switch control circuit 10 shown inFIG. 4 uses inverters as the clock buffers that generate the controlclocks N3, N4. However, as shown in FIG. 6, non-inverting buffers 203,204 may be used in place of the above-mentioned inverters.

FIG. 6 is a diagram illustrating another example configuration of theswitch control circuit 10 according to an embodiment of the presentinvention. Referring to FIG. 6, the switch control circuit 10 includesinverters 101, 102 and non-inverting buffers 203, 204, and generatescontrol clocks N1, N2, N3, and N4 in accordance with an input clock CLK.

More specifically, the inverter 101 inverts the signal level of theinput clock CLK, and outputs the inverted clock to the inverter 102,non-inverting buffer 204, and D-FF circuit as the control clock N2. Theinverter 102 inverts the signal level of the input control clock N2, andoutputs the inverted clock to the non-inverting buffer 203 and D-FFcircuit as the control clock N1. The non-inverting buffer 203 buffersthe input control clock N1 to obtain the control clock N4, and thenoutputs the control clock N4 to the D-FF circuit. The non-invertingbuffer 204 buffers the input control clock N2 to obtain the controlclock N3, and then outputs the control clock N3 to the D-FF circuit.

In the example shown in FIG. 6, outputs N3 and N4 are interchangedbecause the buffers 203, 204 are used in place of the inverters 103,104. Operations concerning the other timing adjustments are the same asdescribed above. The non-inverting buffers 203, 204 include an evennumber of (usually two) cascade-coupled inverters. Therefore, the amountof delay of the control clocks N3, N4 relative to the control clocks N1,N2 is increased so that operations can be performed even when the setuptime is shorter than in the example described earlier. Further, as therise time and fall time (tr, tf) of the control clocks N3, N4 can bedecreased, higher-speed operations can be handled. Furthermore, the loadcapacitance as viewed from the inverters 101, 102 is limited to thefirst-stage inverters of the buffers 203, 204. Therefore, even if thedimensions of transistors forming the output stages of the buffers 203,204 are changed in order to provide a different driving capacity, theload capacitances of the inverters 101, 102 remain unchanged. Thiseliminates the influence on the control clocks N1, N2 and provides anadvantage in that the setup time can be adjusted with ease.

Although the CMOS transfer gate 12, which is based on a CMOS transistor,is described as an input control switch of the data DATA for the masterFF 2 with reference to FIG. 3, the present invention is not limited tosuch a configuration. A switch circuit having a different configurationmay alternatively be used. Moreover, a clocked inverter 13 whoseoperation is controlled by the control clocks N3, N4 may be used inplace of the inverter 11 and CMOS transfer gate 12 shown in FIG. 3.

FIG. 7 is a diagram illustrating another example configuration of theD-FF circuit according to an embodiment of the present invention. TheD-FF circuit shown in FIG. 7 includes an input buffer 1, which includesa clocked inverter 13. The other elements are the same as for the D-FFcircuit shown in FIG. 3.

The clocked inverter 13 inverts the signal level (logic value) of inputdata and outputs the inverted data to the input terminal Nin of themaster FF 2. More specifically, the clocked inverter 13 turns on whenthe control clock N3 is at the “H” level and the control clock N4 is atthe “L” level, and outputs the inverted data of the data DATA to theinput terminal Nin of the master FF 2. Further, the clocked inverter 13turns off when the control clock N3 is at the “L” level and the controlclock N4 is at the “H” level, and places the input terminal Nin of themaster FF 2 in a high-impedance state.

The operations of the D-FF circuit shown in FIG. 7 are the same asdescribed earlier. Further, the D-FF circuit shown in FIG. 7 facilitatesthe timing adjustments as described earlier. However, the layout area ofthe clocked inverter is at an advantage in that it is smaller than thelayout area of a transfer gate. More specifically, the input buffer 1shown in FIG. 3 needs to be configured in such a manner that thetransistors for the inverter 11 and CMOS transfer gate 12 are separatelyformed. On the other hand, the clocked inverter 13 can be configured sothat a diffusion layer is shared by a switch transistor, which providesswitching control in accordance with the control clocks N3, N4, and aninverter transistor, which inverts a signal. Therefore, using theclocked inverter 13 as the input buffer 1 makes it possible to reducethe area of the input buffer 1.

The above-described D-FF circuit and switch control circuit 10 can becombined as far as no technical discrepancy arises. Further, althoughthe D-FF circuit operating at the rising edge is described as an examplewith reference to FIGS. 5A and 5B, the present invention is alsoapplicable to the D-FF circuit operating at the falling edge.Furthermore, in the example described earlier, the master FF 2, the M-Sswitch 3, and the slave FF 4 operate in synchronism with the samecontrol clocks N1, N2. However, the present invention is not limited tosuch a situation. The present invention is also applicable to asituation where the master FF 2, the M-S switch 3, and the slave FF 4operate in synchronism with different control clocks as far as theydiffer from the control clocks N3, N4.

In an embodiment of the present invention, the load capacitance asviewed from the clock buffers in the switch control circuit 10 is lowerthan before because it results from the input buffer 1 only. Therefore,even when the gate width of a transistor forming the input controlswitch (CMOS transfer gate 12 or clocked inverter 13) is increased toshorten the delay time in the input buffer 1, it is possible to suppressan increase in the sizes of the clock buffers. Further, the clockbuffers (inverters 103, 104 or non-inverting buffers 203, 204) thatdouble as delay elements are merely expected to drive the gate of anN-channel MOS transistor or P-channel MOS transistor forming the inputcontrol switch (CMOS transfer gate 12 or clocked inverter 13).Therefore, even when the transistor size is reduced for timingadjustment purposes, the influence on the overall layout size is small.In addition, the influence on the other components (not shown) coupledto the clock buffers is limited. Consequently, the setup time can beadjusted with ease.

What is claimed is:
 1. A method to control a D-FF circuit, comprising: choosing to output an input data signal or output a high impedance signal in accordance with supplying a first control clock to an input buffer; choosing to output a data signal received from the input buffer or retain a currently output data signal in accordance with supplying a second control clock to a master flip-flop; choosing to output a high-impedance signal or output a data signal received from the master flip-flop in accordance with supplying the second control clock to a master-slave switch; choosing to retain a currently output data signal or output a data signal received from the master-slave switch in accordance with supplying the second control clock to a slave flip-flop; outputting the second control clock in accordance with supplying an external clock to a first clock buffer; and outputting the first control clock retards rising and/or falling edges of the second control clock in accordance with supplying the second control clock to a second clock buffer, wherein the input buffer does not receive the second control clock, and wherein none of the master flip-flop, the master-slave switch, and the slave flip-flop receive the first control clock.
 2. The method according to claim 1, wherein the input buffer includes a clocked inverter, which operates in accordance with the first control clock, inputs an input data signal, and outputs the first data signal.
 3. The method to claim 1, further comprising: generating and outputting the first control clock based on the second control clock.
 4. The method according to claim 1, wherein the first control clock comprises a first pair of complementary clocks, and wherein the second control clock comprises a second pair of complementary clocks. 